The mechanisms of void formation and Void elimination during the stamping process of a polypropylene/glass fiber composite have been infestigated as a function of temperature, pressure, and time. Experiments were performed in a temperature and pressure controlled chamber, equipped with a rapid cooling facility.
Samples of the composite as well as model polypropylene specimens containing calibrated voids were held at 200°C at different levels of hydrostatic pressure (1,10,100, and 300 bars), for a period of either 1 or 10 min. The speciments were subsequently characterized by denstiy measurements and morphologival observation.
It was shown that: i) the expansion of the composite observed during the heating at 200°C under atmospheric pressure is largely induced by the gases previously dissolved in the polymeric matrix, ii) the rapid increase of the pressure during the stamping process leads to the closing of voids and, iii) the final holding under high calculation of void growth and shrinkage is in agreement with the morphological observations.
This paper describes the research completed to qualify materials to be used as bottom anti-reflective coatings (BARCs) for dual damascene (DD) photolithography. Several problems have been identified in the DD process. Among them are low fill, iso-dense bias, meniscus shape, via wall coating, and void formation. The issue focused upon in this research is incomplete displacement or void formation in the vias. These voids will have detrimental effects and could ultimately cause chip failure.
Interfacial reaction under in a confined space is becoming an increasingly important issue, due to its applications for wafer bonding in three-dimensional integrated circuits. This study aims to uncover the space confinement effects on Ni/Sn and Ni/SnAg reactions. Space confinement causes the formation of voids near the center of Ni/Sn/Ni sandwiches. Adding Ag effectively eliminates these voids, which, if present, would undoubtedly degrade the reliability of wafer bonding joints. The mechanism for the formation of these voids is proposed and verified.
Stack chip package design is very popular due to demand of big data processing. In process of stack chip bonding, void elimination between chip and bonding tape is quite important to prevent delamination and chip cracks.
Air compression is very effective to eliminate void since the void is compressed from all of the direction in the pressure vessel. Besides, high temperature process is available to cure the adhesion in the same process.
When less than require solder is applied to a joint, it can result in empty spaces or holes inside the solder joint – these are known as Solder Voids. A Solder void is generated due to the insufficient availability of solder while creating the joint
Increasing soak time will reduce voiding for some solder pastes. Increasing soak time will drive off more of the low boiling volatiles from the solder paste prior to reflow. Increasing peak temperature will reduce voiding for some solder pastes. Read More
